Embodiments of the present invention relate to a processor-based system, and more particularly to a system including multiple sequencers of different instruction set architectures.
Computer systems include various components to process and communicate data. Typical systems include one or multiple processors, each of which may include multiple cores, along with associated memories, input/output (I/O) devices and other such components. To improve computation efficiencies, computation accelerators, special-purpose I/O devices and other such specialized units may be provided via one or more specialized components, referred to generically herein as helper units. However, inefficiencies may occur in using such helper units, as in a typical computing environment that implements a general-purpose processor and an industry-standard operating system (OS) environment, a software stack can impede efficient usage. That is, in a typical OS environment, system software is isolated from application software via different privilege levels, and operations in each of these different privilege levels are subject to OS context save and restore operations, among other limitations. Further, helper units typically lack the ability to handle processing of exceptions and faults that allow robust handling of certain events during execution.
Classic examples of a computation accelerator are coprocessors such as math coprocessors like so-called x87 floating point coprocessors for early Intel® Architecture (IA)-32 processors. Typically, such coprocessors are coupled to a main processor (e.g., a central processing unit (CPU)) via a coprocessor interface, which is of a common instruction set architecture (ISA) as the main processor. More recently, separate resources having different instruction set architectures (ISAs) have appeared in systems.
Where multiple resources of different ISAs are present in a system that runs a single image OS (e.g., industry-standard OS) written for a single ISA, typically limited or no support for handling exceptions or faults incurred during code execution on the resource(s) of a heterogeneous ISA is afforded. Even if such handling were present, potentially disparate architectural mechanisms of the different ISAs would require major rewriting of the OS. As a result, heterogeneous resources generally do not provide support for exception and fault handling, which diminishes their suitability for various tasks.